ISL51002CQZ-110【PDF 26/33 页】IC FRONT END 10BIT VID 128-MQFP

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FN6164.3

February 29, 2012

FIGURE 7. CONFIGURATION REGISTER READ

ISL51002 Serial Bus Address Write

This is the 7-bit address of the ISL51002 on the 2-wire bus. The

address is 0x98 if pin 67 is low, 0x9A if pin 67 is high. R/W = 0,

indicating next transaction will be a write.

(PIN 67)

R/W

ISL51002 Register Address Write

This sets the initial address of the ISL51002’s configuration

ISL51002 SERIAL BUS ADDRESS

START COMMAND

Signals the beginning of serial I/O

ISL51002 Serial Bus Address Write

This is the 7-bit address of the ISL51002 on the 2-wire bus. The

address is 0x98 if pin 67 is low, 0x9A if pin 67 is high. R/W = 1,

indicating next transaction(s) will be a read.

ISL51002 Register Data Read(s)

This is the data read from the ISL51002’s configuration register.

Note: The ISL51002’s Configuration Register’s address pointer

auto increments after each data read: repeat this step to read

multiple sequential bytes of data from the Configuration Register.

(PIN 67)

R/W

ISL51002 SERIAL BUS

START COMMAND

STOP COMMAND

(REPEAT IF DESIRED)

Ends the previous transaction and starts a new one

Signals the ending of serial I/O

DATA

READ*

SDA BUS

SIGNALS

FROM THE

ISL51002

SIGNALS

FROM THE

HOST

REGISTER

ADDRESS

SERIAL BUS

ADDRESS

aaaaaaaa

dddddddd

100110 A 0

* The data read step may be repeated to read

from the ISL51002’s Configuration Register

sequentially, beginning at the Register

Address written in the two steps previous.

SERIAL BUS

ADDRESS

100110 A 1

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web

to make sure you have the latest revision.

DATE

REVISION

CHANGE

November 17, 2011

FN6164.3

Added “Revision History” table.

Changed description of ISL51002's input multiplexer from 4 channels to 3 channels due to discovery of

significant signal leakage between channel 3 and channel 1 when channel 3 was selected. This is not a

silicon change - all ISL51002s have always had this issue; it was not discovered until recently.

ISL51002

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